This invention relates generally to semiconductor wafer testing and more particularly to a test signal generator and method for testing a semiconductor wafer having a plurality of memory chips.
Semiconductor memory devices, such as dynamic random access memory (DRAM) and static random access memory (SRAM) devices, are integrated circuit (IC) chips fabricated on a semiconductor wafer. During the manufacturing process, these devices are subjected to various tests to ensure their reliability.
Memory device reliability tests are generally classified into either a wafer test performed before chip packaging or a package test performed after packaging. Both forms of testing are well-known in the field. The wafer test employs a simple test pattern to check whether the memory cells and peripheral circuits in each chip are working normally. The package test checks the internal circuitry of each chip against the fundamental timing signals represented in the memory specification and other signals to ascertain whether the chip passes or fails.
Test coverage and testing time are important factors to be considered in satisfactorily performing these tests. Test coverage is related to the reliability of the memory device and the testing time to the yield rate of production. Moreover, testing time increases with the level of integration of the chip and thereby causes an increase in overall production time and chip costs.
To this end, there has been proposed a multi-chip test method which simultaneously tests all of the memory chips on a semiconductor wafer. However, for testing high speed, large scale semiconductor memory devices which each support various functions including multiple data input/output terminals, e.g., multiple DQ, X16, X32 terminals, and multiple function signal input/output terminals, the method is limited by the number of available pins. Consequently, when testing a semiconductor wafer having a plurality of memory chips using this multi-chip test method, the test can only drive the available pins and the number of memory chips tested is thereby reduced.
Referring to FIG. 1, a block diagram of a prior art conventional test signal generator using the multi-chip test method for supplying a test signal to a semiconductor wafer is shown. Normally, to perform the wafer test, the pads for each memory chip to which such functional pins will be connected must be supplied with a direct current signal of a level through the tip on a probe card or the contact pins of a membrane card. Test timing signals for a test pattern are set to a direct current of a logic "high" or "low," such as the source or ground voltage level. These signals do not operate as row or column strobe signals, rather they are applied to the pad (or pins) defining the specific functions of the memory chip. For example, a typical eight megabyte synchronous graphic DRAM has functional pins, such as DQM, DSF (Define Special Function), CKE and so on, which are configured to receive an input signal of logic "high" or "low."
As show in FIG. 1, a memory chip 10, one of a plurality of memory chips fabricated on a semiconductor wafer (not shown), includes a pad 14 for receiving a test timing signal of logic "low" or "high" during a wafer test to establish the operational modes of the peripheral circuits of the chip. A probe tip on a probe card 12 supplies a direct current of a logic "high" or "low" to the pad 14 of the chip. When performing the wafer test, the probe tips on the probe card 12 are supplied with the direct current at the desired level. This is to maintain the pads at a the desired voltage level to test the operational states of the internal circuits of the memory chips on the semiconductor wafer. The pad 14 is also connected through a signal line to an input buffer 16 for transferring the input signal to the internal circuits of the memory chip 10.
The probe card 12 and wafer are paired to perform the test with the desired test pattern. The probe card 12 has a fixed number of tips corresponding to the total number of pads on the memory chips 10 fabricated on the semiconductor wafer. Consequently, due to its fixed number of tips, the probe card 12 is unusable for testing other wafers having more pads.
Therefore, what is needed is a memory device test signal generator for testing semiconductor wafers comprising memory chips having different pad configurations.